The present invention is directed to clamped inductive load circuits and, more particularly, to clamped inductive load circuits in which a MOS gate controlled ("MOS-gated") power transistor is switched on and off wherein the circuitry is integrated into a silicon chip.
Power transistor devices, while turning on or off, divert the flow of current and reconfigure the voltage distribution of a power conversion circuit. MOS-gated transistors, such as MOSFETs or IGBTs, perform this operation within a fraction of a microsecond at very rapid voltage and current slew rates. The fast switching of their waveforms are desirable for reducing switching losses and for increasing operating frequency but also have the adverse effect of generating unwanted electromagnetic interference (EMI) in the surrounding environment. In environments where EMI susceptibility is critical or where EMI interference is regulated by legislation, it is desirable to independently adjust the voltage and current waveforms to meet these requirements without unnecessarily increasing the switching losses.
A clamped inductive load circuit is a power circuit whose load inductance prevents its current from being brought to zero within a cycle of the operating frequency. Most power conversion circuits are clamped inductive load circuits. FIG. 1A shows a simplified clamped inductive load circuit in which a MOSFET 103 goes in and out of conduction. The switching transient can be divided into a number of intervals, as shown in FIG. 1B and 1C, wherein the current rise interval and the voltage fall interval follow each other and can be controlled independently.
While the gate drive circuit feeds current to the gate, the gate voltage rises in the manner of a capacitor being charged, shown as interval 1 in FIG. 1B. When the gate voltage V.sub.gs reaches the threshold voltage of the MOSFET 103, the drain current I.sub.DRAIN increases and diverts current away from the freewheeling diode 102, as shown in interval 2. As long as the diode 102 carries current, the drain voltage is clamped to the supply voltage. When all the current (plus reverse recovery current, if any) is transferred from the diode to the MOSFET, the drain voltage falls to its final, fully enhanced, value. Hence, the drain voltage only begins to fall after the drain current rise is completed which allows separate control of both waveforms. This process is described in detail in International Rectifier Application note AN-944: "A New Gate Charge Factor Leads to Easy Drive Design for Power MOSFET Circuits".
During the drain current rise, shown in interval 2 of FIG. 18, the drain current is proportional to the gate voltage, and the rate of rise of the gate voltage determines the switching di/dt. Because of the gate capacitance of MOSFET 103 (capacitor 103B), the current rise time can be controlled by controlling the quantity of current supplied to the gate. The reverse recovery of the diode prolongs interval 2.
During the drain voltage fall, shown as interval 3, the output capacitor 103A and the reverse transfer capacitor 103C of MOSFET 103 discharge. The rate at which these two capacitances are discharged determine the rate at which the drain voltage falls. While the output capacitor discharges rapidly through the channel resistance, the reverse transfer capacitor only discharges through the gate drive circuit. The flat portion of the gate voltage curve shown in interval 3 indicates that the current supplied to the gate terminal is almost completely delivered to the reverse transfer capacitor whereas the voltage across the input capacitor does not change. Thus, the value of the dv/dt here can be controlled by supplying an appropriate amount of current to the gate.
At the end of interval 3 in FIG 1B, the switching transient is completed and any additional current supplied to the gate does not change the drain voltage or drain current, as shown in interval 4 of FIG 1B.
The turn-off process is generally a mirror image of the turn-on process. First, the gate voltage V.sub.gs is reduced to a value that barely maintains the drain current, as depicted in interval 1 of FIG. 1C. Then, the voltage across the device rises, while the drain current is constant, as shown in interval 2 of FIG 1C. When the voltage across the MOSFET 103 exceeds the supply voltage by a value equal to the diode voltage drop, the diode starts conducting and load current is transferred from the MOSFET through the diode, as shown in interval 3 of FIG 1C. As the device turns on, the rise in drain voltage and the fall in drain current occur sequentially. The drain voltage rise time is thus substantially determined by the charging of the reverse transfer capacitor through the gate circuit impedance 104, and the subsequent drain current fall time is determined by the discharging of the input capacitance. A voltage overshoot is often present at the drain when interval 2 ends which prolongs this interval.
MOS-gated devices with a significant minority carrier component of current, such as IGBTs, MCTs and other derivatives, behave somewhat differently at turn-off because their current fall time is influenced by the recombination of the minority carriers. Similarly, the current rise time during their turn-on is influenced by the carrier injection efficiency.
Typically, resistors are incorporated into the gate drive circuit to slow down the switching. An additional resistor 201 and diode 202, as shown in FIG. 2A, may be added to the circuit of FIG. 1A to change the wave form at turn-on and at turn-off and, particularly, to limit the reverse recovery current from the diode. Because different respective current values are needed to obtain the desired di/dt and dv/dt, the selection of the added resistor requires a compromise between obtaining the desired di/dt and obtaining the desired dv/dt. The added resistors in the gate drive circuit also make the circuit more prone to dv/dt induced turn-on, namely an unwanted conduction caused by a transient current in the drain that is coupled to the gate through the reverse transfer capacitance.
By contrast, the diode 202 shunts the resistor 201 shown in FIG. 2A and bypasses the resistor, thus providing a low impedance path for fast transients injected from the drain, but eliminates the possibility of providing turn-off waveshaping.
As shown in FIG. 2B, resistor 211 and diode 212 may be used as in FIG. 2a for resistor 201 and diode 202, respectively, but a resistor 216 is further connected in series with diode 212 for further control.
Control of dv/dt is attempted by Siliconix in the a gate driver IC Si9910 sold by Siliconix Corporation. Thus, as shown in FIG. 3, the voltage slew rate is sensed using a small capacitance 308 connected to the drain of power device 310. The sensed dv/dt is controlled by a feedback loop. The circuit however, uses a linear loop which is prone to oscillations. The chip also provides control of the peak current, but di/dt in the power device is controlled only when appropriate feedback is provided.
Additionally, the short-circuit protection scheme used in the circuit of FIG. 3 typically turns off the power transistor in two steps to avoid voltage overshoots frequently associated with fast turn-off of a large current. Thus, the gate voltage is initially reduced to approximately half its initial value and then is totally shut off. This approach allows a power device to be turned off slowly, rather than in two steps, from a short circuit condition. The circuit, however, does not control di/dt during switching because it is intended to protect the device from the overvoltage transient associated with the turn-off of a fault, such as short circuit, and is triggered by the fault and is otherwise inoperative during normal operation. Such methods are also described in "IGBT Fault Current Limiting Circuit" by R. Chokhawala and G. Castino, IR IGBT Data Book IGBT-3, page E-127.
It therefore is desirable to provide a circuit which both drives a MOS-gated power transistor device and controls both the switching di/dt and the switching dv/dt.